[SD] How to Use MMC/SDC
Posted: 14-Apr-2014, 19:04
How to Use MMC/SDC
The Secure Digital Memory Card (SDC below) is the standard memory card for mobile equipments. The SDC was developped as upper-compatible to Multi Media Card (MMC below). SDC compleant equipments can also use MMCs in most case. There are also reduced size versions, such as RS-MMC, miniSD and microSD, with the same function. The MMC/SDC has a microcontroller in it. The flash memory controls (erasing, reading, writing, error controls and wearleveling) are completed inside of the memory card. The data is transferred between the memory card and the host controller as data blocks in unit of 512 bytes, so that it can be seen like a generic hard disk drives from view point of upper level layers. The currentry defined file system for the memory card is FAT12/16 with FDISK patitioning rule. The FAT32 is defined for only high capacity (>= 4G) cards.
Pinout
The MMC has seven contact pads and the SDC has nine contact pads that two additional contacts to the MMC. The three of the contacts are assigned for power supply so that the number of effective signals are four (MMC) and six (SDC). Therfore the data transfer between the host and the card is done via a synchronous serial interface. The working supply voltage range is indicated in the operation conditions register (OCR) and it should be read and comfirmed the operating voltage range. However, the supply voltage can be fixed to 3.0/3.3 volts because the all MMC/SDCs work at supply voltage of 2.7 to 3.6 volts at least. The current consumption on write operation can reach up to some ten miliamperes, so that the host system should consider to supply 100 miliamperes to tha card.
SPI Mode
This document describes the protocol to control MMC/SDCs in SPI mode. The SPI mode is an alternative operating mode that defined to use the MMC/SDCs without native host interface. The communication protocol for the SPI mode is a little simple compared to its native operating mode. The MMC/SDC can be attached to the most microcontrollers via a generic SPI interface or GPIO ports. Therefore the SPI mode is suitable for low cost embedded applications with no native host interface is available. There are four different SPI modes, 0 to 3, depends on clock phase and polarity. Mode 0 is defined for SDC. For the MMC, it is not the SPI timing, both latch and shift actions are defined with rising edge of the SCLK, but it seems to work at mode 0 in the SPI mode. Thus the Mode 0 (CPHA=0, CPOL=0) is the proper setting to control MMC/SDC, but mode 3 (CPHA=1, CPOL=1) also works as well in most case.
Command and Response
In SPI mode, the data direction on the signal lines are fixed and the data is transferred in byte oriented serial communication. The command frame from host to card is a fixed length packet that shown below. The card is ready to receive a command frame when it drives DO high. After a command frame is sent to the card, a response to the command (R1, R2, R3 or R7) is sent back from the card. Because the data transfer is driven by serial clock generated by host controller, the host controller must continue to read data, send a 0xFF and get received byte, until a valid response is detected. The DI signal must be kept high during read transfer (send a 0xFF and get the received data). The response is sent back within command response time (NCR), 0 to 8 bytes for SDC, 1 to 8 bytes for MMC. The CS signal must be driven high to low prior to send a command frame and held it low during the transaction (command, response and data transfer if exist). The CRC feature is optional in SPI mode. CRC field in the command frame is not checked by the card. SPI Command Set
Each command is expressed in abbreviation like GO_IDLE_STATE or CMD<n>, <n> is the number of the command index and the value can be 0 to 63. Following table describes only commands that to be usually used for generic read/write and card initialization. For details on all commands, please refer to spec sheets from MMCA and SDCA. SPI Response
There are some command response formats, R1, R2, R3 and R7, depends on the command index. A byte of response, R1, is returned for most commands. The bit field of the R1 response is shown in right image, the value 0x00 means successful. When any error occured, corresponding status bit in the response will be set. The R3/R7 response (R1 + trailing 32-bit data) is for only CMD58 and CMD8. Some commands take a time longer than NCR and it responds R1b. It is an R1 response followed by busy flag (DO is driven to low as long as internal process is in progress). The host controller should wait for end of the process until DO goes high (a 0xFF is received).
The Secure Digital Memory Card (SDC below) is the standard memory card for mobile equipments. The SDC was developped as upper-compatible to Multi Media Card (MMC below). SDC compleant equipments can also use MMCs in most case. There are also reduced size versions, such as RS-MMC, miniSD and microSD, with the same function. The MMC/SDC has a microcontroller in it. The flash memory controls (erasing, reading, writing, error controls and wearleveling) are completed inside of the memory card. The data is transferred between the memory card and the host controller as data blocks in unit of 512 bytes, so that it can be seen like a generic hard disk drives from view point of upper level layers. The currentry defined file system for the memory card is FAT12/16 with FDISK patitioning rule. The FAT32 is defined for only high capacity (>= 4G) cards.
Pinout
The MMC has seven contact pads and the SDC has nine contact pads that two additional contacts to the MMC. The three of the contacts are assigned for power supply so that the number of effective signals are four (MMC) and six (SDC). Therfore the data transfer between the host and the card is done via a synchronous serial interface. The working supply voltage range is indicated in the operation conditions register (OCR) and it should be read and comfirmed the operating voltage range. However, the supply voltage can be fixed to 3.0/3.3 volts because the all MMC/SDCs work at supply voltage of 2.7 to 3.6 volts at least. The current consumption on write operation can reach up to some ten miliamperes, so that the host system should consider to supply 100 miliamperes to tha card.
SPI Mode
This document describes the protocol to control MMC/SDCs in SPI mode. The SPI mode is an alternative operating mode that defined to use the MMC/SDCs without native host interface. The communication protocol for the SPI mode is a little simple compared to its native operating mode. The MMC/SDC can be attached to the most microcontrollers via a generic SPI interface or GPIO ports. Therefore the SPI mode is suitable for low cost embedded applications with no native host interface is available. There are four different SPI modes, 0 to 3, depends on clock phase and polarity. Mode 0 is defined for SDC. For the MMC, it is not the SPI timing, both latch and shift actions are defined with rising edge of the SCLK, but it seems to work at mode 0 in the SPI mode. Thus the Mode 0 (CPHA=0, CPOL=0) is the proper setting to control MMC/SDC, but mode 3 (CPHA=1, CPOL=1) also works as well in most case.
Command and Response
In SPI mode, the data direction on the signal lines are fixed and the data is transferred in byte oriented serial communication. The command frame from host to card is a fixed length packet that shown below. The card is ready to receive a command frame when it drives DO high. After a command frame is sent to the card, a response to the command (R1, R2, R3 or R7) is sent back from the card. Because the data transfer is driven by serial clock generated by host controller, the host controller must continue to read data, send a 0xFF and get received byte, until a valid response is detected. The DI signal must be kept high during read transfer (send a 0xFF and get the received data). The response is sent back within command response time (NCR), 0 to 8 bytes for SDC, 1 to 8 bytes for MMC. The CS signal must be driven high to low prior to send a command frame and held it low during the transaction (command, response and data transfer if exist). The CRC feature is optional in SPI mode. CRC field in the command frame is not checked by the card. SPI Command Set
Each command is expressed in abbreviation like GO_IDLE_STATE or CMD<n>, <n> is the number of the command index and the value can be 0 to 63. Following table describes only commands that to be usually used for generic read/write and card initialization. For details on all commands, please refer to spec sheets from MMCA and SDCA. SPI Response
There are some command response formats, R1, R2, R3 and R7, depends on the command index. A byte of response, R1, is returned for most commands. The bit field of the R1 response is shown in right image, the value 0x00 means successful. When any error occured, corresponding status bit in the response will be set. The R3/R7 response (R1 + trailing 32-bit data) is for only CMD58 and CMD8. Some commands take a time longer than NCR and it responds R1b. It is an R1 response followed by busy flag (DO is driven to low as long as internal process is in progress). The host controller should wait for end of the process until DO goes high (a 0xFF is received).