[FPGA] Special function pins: GCK, GTS, GSR

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Global Clock (GCK) pins
Many high-speed digital logic designs need a clock signal that reaches all components simultaneously. While any CPLD/FPGA pin can input a clock signal and distribute it to the design, GCK pins and their internal connections are optimized for clock signals. They are designed to have minimum skew rates, and that all the connection lengths are the same to allow for perfect synchronicity between devices.

Global tri-state (GTS) pins
The GTS pin is optimized to toggle all the other pins between input and output. This is helpful if you need to disable all the CPLD/FPGA outputs at once.

Global Set/Reset (GSR) pins
When designing projects that use flip-flops it may be necessary to reset all of them simultaneously. The Global Set/Reset (GSR) pins are designed for this purpose.

The dual purpose pins GTS, GCK, GSR, CDRST and DGE can all be used as general user I/O. If the clock divider is used in the design, then CDRST cannot be used as a general purpose I/O, even if the reset port of the clock divider is not used.